next up previous contents
Next: 7.1 Signal Declaration Up: Contents Previous: 6.2 Subprograms

   
7. Signals

VHDL elements at the behavior level (processes, variables and sequential assignments) find their naturally corresponding elements in programming languages. Signals and parallel blocks, on the other hand, have characteristics that are typical for structure-level descriptions and their simulations.

In VHDL signals are the only way to tie together elements of structural descriptions or to enable processes to communicate. They act like wires. In the simulation, signals are handled in a time dependent manner, in the sense that every action is preceded by a cause.



 

Richard Geissler
1998-10-07