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2.8 Simulation

After the successful analysis of VHDL models, their simulation could be performed to verify the correct functionality. For this purpose, the elements in the lowest hierarchy level must be available as behavioral descriptions. Starting point of the simulation is the analyzed configuration declaration of a testbench or the top-level module.

Before the actual simulation takes place, the following two step are executed (without the interaction between the circuit developer and the simulation tool):

1.
Elaboration phase: The most important part of this step is assembling the hierarchy. This is where all entity-architecture pairs are built as specified by the configurations. This is similar to the activities taking place during linking in other programming languages like C. Furthermore, memory is allocated for signals, variables and constants, and their values are initialized as specified.
2.
Initialization phase: All processes are executed once until they get suspended by the first encountered wait statements, or after one complete pass in case of an existing sensitivity_list. Signals are assigned their starting values and the simulation time is set to zero.

The simulation is usually done by stimulating the input signals of the unit under test (UUT) with the appropriate waveforms. This is easily achieved by the so-called testbench, a special entity which resides on top of the complete unit under test. The testbench generates the stimuli waveforms for the input signals of the unit under test by either a behavioral description or by reading them from a file. It is also possible to have the output signals from the UUT read, checked for correctness or written to a file by the testbench. Figure 9 illustrates the testbench concept.


  
Figure 9: Test environment during simulation
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\epsfbox{eps-engl/testben.eps}
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next up previous contents
Next: 3. Data Types Up: 2. Basic VHDL Concepts Previous: 2.7 Analysis of VHDL
Richard Geissler
1998-10-07