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Subsections

2.6 Additional Signal Characteristics

As already mentioned in Section 2.3.2, signals differ from the concept of VHDL variables, as well as variables found in other programming languages. In the following section additional important characteristics of signals are presented.

  
2.6.1 Delay Models

During the VHDL simulation event queues, which contain all future signal events, are created and manipulated. The handling of new generated events and the events already existing in the event queues is influenced by different delay models. Based on the so-called preemption mechanism, actions already existing in the event queue are partially removed when a new event is scheduled.

The following two delay models are distinguished:

transport delay model:
All entries, which are scheduled for the same or later time in the event queue, are deleted. This delay model is specified by the keyword transport in the signal assignment statement.
inertial delay model:
The inertial delay model is the default and the most commonly used one. In this model all entries of the event queue which would be deleted by the transport delay model are also removed. In addition, the following rules are applied:
1.
Mark the entry directly before the new one if it has the same value.
2.
Mark the current and the new entry.
3.
Delete all entries which are not marked.

The consequence of this delay model is that all signal impulses shorter than the delay specified in the signal assignment statement are swallowed.

Figure 6 illustrates the difference between the two delay models with an example. The starting point is a signal SIG which consists of impulses with different durations. Signals SIG_T and SIG_I are generated from the signal SIG by the following two statements:

Statement:
SIG_T <= transportSIG after 3 ns;
SIG_I <=         SIG after 3 ns;


  
Figure 6: Waveforms generated by different delay models.
\begin{figure}
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Due to the specified delay time of 3 ns all impulses shorter than 3 ns are filtered out in case of the inertial delay model. This is illustrated by the signal waveform SIG_I. This behavior is similar to real hardware in which charging an output node of a gate needs some time and, therefore, a spike or glitch cannot propagate through logic gates.

The assumption that a spike does not propagate through a gate if its duration is less than the delay time of the gate is sometimes not accurate enough. Therefore, a third delay model was defined in the newer 1993 VHDL standard in which the delay time and the maximum filtered pulse width can be specified separately.

   
2.6.2 Resolution Functions

Another interesting feature of signals is that multiple signal assignment statements may write onto one signal. This means that there exists more than one driver for such a signal. This feature is necessary for modeling bus systems where normally more than one module can write to a bus. In these cases, the resolution function is used to calculate the resulting value of the signal depending on the values written from all drivers.

The STD_LOGIC_1164 package contains the definition of such a resolution function for the type std_ulogic (u = unresolved) named resolved. Within the declaration of the subtype std_logic an implicit call to the resolution function resolved is defined. Consequently, every new value assigned to a signal of type std_logic first goes through the resolution function. The function calculates the real value of the target signal taking into consideration the values produced by the remaining drivers.


next up previous contents
Next: 2.7 Analysis of VHDL Up: 2. Basic VHDL Concepts Previous: 2.5 Packages
Richard Geissler
1998-10-07