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Next: 7.3 Implicit Type Resolution Up: 7. Signals Previous: 7.1 Signal Declaration

   
7.2 Signal Assignments in Process

In general, processes can communicate with the outside world (other processes, entities...) only through signals, and signal values (for example, output ports) are assigned in processes. There are, however, important factors to keep in mind.

Delay time:
The goal of VHDL description is to simulate real circuits with their respective delays (time constants of electric circuits). These delay values are specified during signal assignment statements. For the circuit simulation this means that new signal values are updated only after the specified delay time elapses.

Syntax:
signal_name <= expression
[after time_expr {,
             expression after time_expr}
];
The delay time specified in the signal assignemt (after...) is considered relative to the simulation time reached before the assignment. Zero delay time is also allowed. In a single signal assignment several delays may be given. The simulation algorithm then arranges the time sequence of the future events in a list (scheduling).

Example:
R   <= "1010";
S   <= '1' after 4 ns, '0' after 7 ns;
T   <= 1 after 1 ns, 3 after 2 ns, 6 after 8 ns;
CLK <= not CLK after 50 ns;
 

Activation of Assignment:
Although signal assignments within a process are surrounded by statements which are processed in sequential order, they are not activated in the same apparent sequential order. Signal assignments are activated once the wait statement of a process is reached. Alternatively, when a process is used with the sensitivity-list, signal assignments occur at the end of the process. This leads to the following consequences:
1.
Within a process signals can not be used as variables for temporary value storage.
2.
There should be only one assignment per signal in a process; thus indicating a single driver.
Due to the peculiarities associated with signal assignments, erroneous circuit behavior is often produced (especially by the VHDL beginners). Therefore, here is one more example on the topic:

Example:
X <= Y;   
both assignments will be processed at the wait statement
Y <= X;   
$ \Rightarrow$ the values of X and Y will be exchanged
wait ...   
$ \Rightarrow$ the sequence of these two statements is irrelevant

V := 1;           V
becomes 1 -- immeditately
S <= V;    S
will be V (also 1) -- at the wait statement
A := S;    A
receives the old value of S -- immediately
wait ...

X <= 1;   
Caution: will be ignored due to the second assignment!
Y <= 3;    Y
will be 3 -- at the wait statement
X <= 2;   
this assignment overwrites the first assignment above:
wait ...   
$ \Rightarrow$ X will be 2 -- at the wait statement


next up previous contents
Next: 7.3 Implicit Type Resolution Up: 7. Signals Previous: 7.1 Signal Declaration
Richard Geissler
1998-10-07