Concurrent statements serve to model the behavior of hardware components where events often occur simultaneously.
- | all processes are active in parallel. |
- | a process defines a region in the code where statements are executed sequentially (similarly to the conventional programming languages). It describes behavior employing sequential algorithms. |
- | a process must contain either a sensitivity-list or explicit wait statements. |
- | within a process, signals belonging to an entity or architecture could be read and assigned new values. |
Example:
process ...
begin
loop beginning of the loop
...
wait ... at least one wait, or a sensitivity-list
...
end loop; end of the loop
end process;
It follows then, that a process must have at least one wait statement, or a process must be declared with a sensitivity-list. The sensitivity-list is functionally equivalent to a waiton... statement appearing at the end of a process.
Example:
process (A, B) sensitivity-list
begin
...
end process;
-- is equivalent to --
process
begin
...
wait on A, B;
end process;
Syntax:
[label:] signal_name <= expression [after time_expr];
The assignment is activated when at least one signal on the right
side of the assignment statement changes.
Example:
architecture VER1 of MUX is
begin
OUTPUT <= A (INDEX);
end VER1;
-- is equivalent to --
architecture VER1 of MUX is
begin
process (A, INDEX)
begin
OUTPUT <= A (INDEX);
end process;
end VER1;
Syntax:
[label:] with expression select
signal_name <=expression when value{,
expression when value};
The selected signal assignment is activated as soon as one of the
signals belonging to the selection condition or expression changes.
Example:
with MYSEL select
Z <= A when 15,
B when 22,
C when 28;
Example:
architecture ...
procedure VEC2INT
( signal S: in bit_vector;
signal ZFLAG: out boolean;
signal Q: inout integer;) is
...
begin
VEC2INT (BITVEC, FLAG, NUMBER);
...
-- is equivalent to --
architecture ...
procedure VEC2INT ... declaration, same as above
begin
process (BITVEC, NUMBER)
begin
VEC2INT (BITVEC, FLAG, NUMBER);
end process;
...
A guarded block contains an additional boolean expression guard_expression, which drives an implicit signal GUARD of boolean type. This signal can be used within a block for the control of concurrent assignments. If concurrent statements have an associated GUARD signal, they are known as Guarded Signal Assignments.
Syntax:
label: block [(guard_expression)]
[use_clause]
[subprogram_decl subprogram_body]
[type_decl]
[subtype_decl]
[constant_decl]
[signal_decl]
[component_decl]
begin
[concurrent_statements]
end block [label];
Syntax:
[label:] signal_name <= guarded expression [after time_expr];
Syntax:
[label:] signal_name <=expression when condition else
{expression when condition else}
expression;
The conditional signal assignment is activated as soon as one of the
signals belonging to the condition or expression changes.
Example:
Z <= A when (X > 3) else
B when (X < 3) else
C;