While VHDL designs are structurally connected to the environment through the input and output signals, their behavior can be altered through generic values, which are treated somewhat like variables.
For example, this mechanism allows definitions of the elements'
delay times to take place outside an entity. Thus, in order to
update the component library (for instance, when switching from
1.0m to 0.7
m process), a vendor needs only to specify new
transition times of the components without modifying their behavioral
descriptions.
Generic values appear in the entity declaration prior to the declaration of input and output ports. They can be used as constants in the corresponding architecture.9 The passing and assignment of generic values can be done in the following places:
1. | a default value in the entity declaration |
2. | a default value in the component declaration in the architecture or in the package |
3. | a value can be mapped in the architecture, in the component instantiation |
4. | a value can be mapped in the configuration of the architecture |
Generics are mapped to the actual values using this notation:
declaration_name => actual_value.
Syntax:
-- Declaration inside an entity or a component --
generic ( generic_name : type_name [:= default_value]{;
generic_name : type_name [:= default_value]} );
-- Instantiation --
component_label: component_name
generic map (value_mapping)
port map (signal_mapping);
Cell libraries usually contain generic values along with the declaration of components in separate packages. Furthermore, generics may be specified in configurations. This way, different configurations can be investigated, in order to examine various (min-, typ-, max-delay) implementations.
Example:
entity XR2 is
generic (DELAY: time := 1.0 ns); default delay time as a parameter
port (X, Y: in bit; Z: out bit);
end XR2;
...
architecture GENERAL of XR2 is
begin
Z <= X xor Y after DELAY; use as a constant
end GENERAL;
-- instantiation with a generic values --
architecture S of COMPARE is
signal I: bit;
component XR2
generic (DELAY: time);
port (X, Y: in bit; Z: out bit);
end component;
...
begin
U0: XR2 generic map (DELAY => 1.5 ns)
port map (A, B, I);
...
end S;
-- a generic value in the component declaration --
architecture S of COMPARE is
signal I: bit;
component XR2
generic (DELAY: time := 1.5 ns);
port (X, Y: in bit; Z: out bit);
end component;
...
begin
U0: XR2 port map (A, B, I);
...
end S;
-- a generic value in the component declaration within a package --
package XYZ_COMPONENTS is
component XR2
generic (DELAY: time := 1.5 ns);
port (X, Y: in bit; Z: out bit);
end component;
...
end XYZ_COMPONENTS;
-- a generic value in the configuration --
configuration CFG_LATE of COMPARE is
for S
for U0: XR2 use entity WORK.XR2(GENERAL)
generic map (DELAY => 1.5 ns);
end for;
end for;
end CFG_LATE;