Every data object, such as a constant, variable or signal, stores a value of the given type: integer, real or bit. The type is specified in the object's declaration. VHDL is a strongly typed language. This means that operations and assignments are allowed only if the types of the operands and the result match. In case of mismatch the use of conversion functions is required.
Among the basic types of the STANDARD package, which are always recognized by the VHDL, the types of the following two packages are explained:
std_logic_1164 | in library | IEEE |
textio | in library | STD |