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7.1 Signal Declaration

In VHDL code signals may be declared:

1.
within a package for global signals.
2.
as ports ... in the entity declaration for entity-global signals.
3.
within an architecture as architecture-global signals.

Syntax:
in package or architecture
signal signal_name: type_name
[:= expression];

as a port of an entity
... signal_name: in
|out|inout|buffer type_name;
When ports of an entity are declared, direction of the information flow must be specified:


in input -- read port; such signals may appear only on the right side of variable/signal assignment.
out output -- write port; must be used on the left hand side of a signal assignment.
inout bidirectional wire; no restriction in the usage.
buffer generally, it is an output port (driver); however, it may be used on the right hand side of assignments.

Example:
package SIGDECL is
  signal VCC: std_logic := '1';      
global signals
  signal GND: std_logic := '0';
end SIGDECL;

entity MUXFF is                entity
-global signals
  port (  DIN, SEL, CLK: in bit;
          DOUT: buffer bit);         
used internally
  signal NOUT: bit;
end MUXFF;
...

architecture STRUCT of MUXFF is
  signal MOUT: bit;       architecture
-global signal
begin
  ...

\begin{picture}(336,123)(18,702)
\thicklines
\put(165,750){\framebox (39,54){}}...
...( 18,759){\makebox(0,0)[lb]{\raisebox{0pt}[0pt][0pt]{\tentt DIN}}}
\end{picture}


next up previous contents
Next: 7.2 Signal Assignments in Up: 7. Signals Previous: 7. Signals
Richard Geissler
1998-10-07