The purpose of VHDL descriptions is to provide a model for digital circuits and systems. This abstract view of the real physical circuit is referred to as entity. An entity normally consists of five basic elements, or design units, shown in Figure 1.
In VHDL one generally distinguishes between the external view of a module and its internal description. The external view is reflected in the entity declaration which represents an interface description of a 'black box'. The important part of this interface description consists of signals over which the individual modules communicate with each other.
The internal view of a module and, therefore, its functionality is described in the architecture body. This can be achieved in various ways. One possibility is given by coding a behavioral description with a set of concurrent or sequential statements. Another possibility is a structural description which serves as a base for the hierarchically designed circuit architectures. Naturally, these two kinds of architectures can also be combined. The lowest hierarchy level, however, must consist of behavioral descriptions. One of the major VHDL features is the capability to deal with multiple different architectural bodies belonging to the same entity declaration. In this case, it is necessary to bind one architecture to the entity in order to have a unique hierarchy for simulation or synthesis.
Being able to investigate different architectural alternatives permits the development of systems to be done in an efficient top-down manner. The ease of switching between different architectures has another advantage, namely, quick testing. This also includes switching between behavioral descriptions based on different algorithms, as well as switching to gate-level netlists, for example, after a partial synthesis is performed.
Which architecture should be used for simulation or synthesis in conjunction with a given entity is specified in the configuration section. If the architecture body consists of a structural description, then the binding of architectures and entities of the instantiated submodules, the so-called components, can also be fixed by the configuration statement.
The package is the last element mentioned here. It contains declarations of frequently used data types, components, functions, and so on. The package consists of a package declaration and a package body. The declaration is used, like the name implies, for declaring the above mentioned objects. This means, they become visible to other design units. In the package body, the definition of these objects can be carried out, for example, the definition of functions or the assignment of a value to a constant. Packages are language elements which can be compared with header files and the belonging codes, or object files, found in the programming language C. The partitioning of a package into its declaration and body provides advantages in compiling the model descriptions. This is further elaborated in section 2.7.