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6.1 Assignments

Signal Assignments:
Signal assignments within processes are covered in detail in section 7.2, page [*]. Although signal assignments may appear in the sequential order within a process, the way they are handled during the simulation does not necessarily follow that order.
Variable Assignment:
changes the value of a variable. Both variable and expression types must be compatible, otherwise conversion functions or attributes must be employed.

Syntax:
variable := expression;

If:
is a flow control statement for conditional execution of sequential statements. In the hardware sense it represents simple decoding.

Syntax:
if condition then
  sequential_statements
{elsif condition then
  sequential_statements}
[else
  sequential_statements
]
end if;

Case:
executes one of several sequences of statements depending on the value of expression. In the hardware sense it means decoding of complex codes, for example, buses.

Syntax:
case expression is
  {when choices => sequential_statements}
end case;

choices
must be of the following types:
value => sequential_statements   
exactly one value
value1
| value2 ... => sequential_statements
                                     
Range of values
value1 to value2 => sequential_statements   
chosen range
others => sequential_statements   
remaining range
All possible values of expression must be covered by the set of choices. Alternatively, whenothers could be used as a last statement matching the remaining (uncovered) choices.

Example:
case BCD is                
Decoder: BCD to 7-Segment
  when "0000" => LED := "1111110";
  when "0001" => LED := "1100000";
  when "0010" => LED := "1011011";
  when "0011" => LED := "1110011";
  when "0100" => LED := "1100101";
  when "0101" => LED := "0110111";
  when "0110" => LED := "0111111";
  when "0111" => LED := "1100010";
  when "1000" => LED := "1111111";
  when "1001" => LED := "1110111";
  when others => LED := "----";   don't care
end case;

Loop:
allows repeated execution of a sequence of statements; represents repetition of elements (for example, corresponding to the bit-width) in hardware.

Syntax:
[loop_label:] while condition loop |   with condition test
[loop_label:] for identifier in value1 to value2 loop |   counter
[loop_label:] loop     forever loop...
  sequential_statements
end loop
[loop_label];
The identifier of the for-loop doesn't need to be declared anywhere; it serves as a local variable of the loop. Value assignments to the identifier are not possible.

Next:
statement forces the current loop iteration to terminate. Additional conditions associated with the termination may be specified.

Syntax:
next
[loop_label][when condition];

Example:
for I in 0 to MAX_LIM loop
  if (DONE(I) = true) then next;    
Jump to end loop
  end if;
  Q(I) <= A(I);
end loop;

L1: while J < 10 loop                     
outer loop
  L2: while K < 20 loop                   
inner loop
    ...
    next L1 when J = K;   
jump out of the inner loop
    ...
  end loop L2;
end loop L1;                       
jump destination

Exit:
terminates a loop; optional conditions may be specified.

Syntax:
exit
[loop_label][when condition];

Example:
for I in 0 to MAX_LIM loop
  if (Q(I) <= 0) then exit;     
jump out of the loop
  end if;
  Q(I) <= (A * I);
end loop;
...                                
jump destination

Assert:
allows to check whether certain conditions are satisfied during the program execution under the VHDL-Simulator. This option is helpful for double-checking time restrictions (set-up, hold ...), range constraints, and so on.

Syntax:
assert condition
  
[report string_expr]
  
[severity failure|error|warning|note];
If a condition is evaluated to the boolean false, the user-specified string_expr is displayed along with the severity level indicator.

Example:
process (CLK, DIN)                
behavior of a D-FF
  variable X: integer;
  ...
begin
  ...
  assert (X > 3)
    report "setup violation"
    severity warning;
  ...
end process;

Wait:
dynamically controls execution and suspension of processes. At the behavior level it makes possible to give a realistic representation of a process by modeling signal-dependent activities. Furthermore, through the wait statement signal values are updated in a circuit6.

Syntax:
wait
  
[on signal_name {, signal_name}]
  
[until condition]
  
[for time_expr];
A sensitivity_list of a process is functionally equivalent to the waiton... appearing at the end of the process. There are four different ways to use the wait-statement:


- wait on A, B; :suspends a process until an occurrence of a change is registered. As shown here, execution will resume when a new event is detected on either signal A or B.
- wait until X > 10; :suspends a process until the condition is satisfied; in this case, until the value of a signal X is > 10.
- wait for 10 ns; :suspends a process for the time specified; here, until 10 ns of simulation time elapses.
- wait; :suspends a process indefinitely... Since a VHDL-process is always active, this statement at the end of a process is the only way to suspend it. This technique may be used to execute initialization processes only once.

The example below models an architecture which simulates a Producer/ Consumer problem using two processes. The processes are synchronized through a simple handshake protocol, which has two wires, each with two active states.

Example:
entity PRO_CON is
  ...
end PRO_CON;

architecture BEHAV of PRO_CON is
  signal PROD: boolean := false;   
item produces a semaphore
  signal CONS: boolean := true;   
item consumes a semaphore
begin
  PRODUCER: process                   
producer model
    begin
      PROD <= false;
      wait until CONS;
      ...
produce item
      PROD <= true;
      wait until not CONS;
    end process;
  
  CONSUMER: process                   
consumer model
    begin
      CONS <= true;
      wait until PROD;
      CONS <= false;
      ...
consume item
      wait until not PROD;
    end process;
end BEHAV;


next up previous contents
Next: 6.2 Subprograms Up: 6. Sequential Modeling Previous: 6. Sequential Modeling
Richard Geissler
1998-10-07