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2.2 Entity Declaration

An entity declaration specifies the name of an entity and its interface. This corresponds to the information given by the symbols in traditional design methods based on drawing schematics. Signals which are used for communication with the surrounding modules are called ports.


  
Figure 2: Interface of a full-adder module.
\begin{figure}
\hbox to \textwidth{
\hfill
\epsfbox{eps-engl/ent-fa.eps}
\hfill }
\end{figure}

An entity declaration for the full-adder module shown in Figure 2 is as follows:

Example:
entity FULLADDER is
  - (After a double minus sign (-) the rest of
  - the line is treated as a comment)
  -
  - Interface description of FULLADDER
  port (  A, B, C: in bit;
          SUM, CARRY: out bit);
end FULLADDER;
 

The module FULLADDER has five interface ports. Three of them are the input ports A, B and C indicated by the VHDL keyword in. The remaining two are the output ports SUM and CARRY indicated by out. The signals going through these ports are chosen to be of the type bit. This is one of the predefined types besides integer, real and others types provided by VHDL. The type bit consists of the two characters '0' and '1' and represents the binary logic values of the signals.

Every port declaration implicitly creates a signal with the name and type specified. It can be used in all architectures belonging to the entity in one of the following port modes:

Mode in:
The port can only be read within the entity and its architectures.
Mode out:
This port can only be written.
Mode inout:
This port can be read and written. This is useful for modeling bus systems.
Mode buffer:
The port can be read and written. Each port must have only one driver.

In order to improve the re-usability of VHDL codes these descriptions can be implemented with parameters, known as generics. For example, in a large hierarchical design it efficient to describe a register with an unconstrained bit width only once, and instantiate it in a structural description with the desired bit width specified by a generic. The entity declaration for such a register is given below:

Example:
entity DFF is
  - parameter: width of the data
  generic (width: integer);
  - input and output signals
  port (  CLK, NR: in bit;
          D: in bit_vector(1 to width);
          Q: out bit_vector(1 to width));
end DFF;
 

The parameter width affects the width of the input bus D and the output bus Q. These buses are declared as bit_vector(1 to width) which is equivalent to an array of signals (the number of elements in the array is specified by width) of the type bit, whose elements can be accessed by the index 1, 2, ..., width.

In general, the entity declaration has the following format:

Syntax:
entity entity_name is
  
[generics]
  
[ports]
  
[declarations (types, constants, signals)]
  
[definitions (functions, procedures)]
[begin                              - normally not used
  statements
]
end
[entity_name];

A detailed description of generic and port declarations syntax is found in Section 2.3.3. The above examples can be used as templates. Besides the declaration of generics and ports, it is possible to declare types, constants, functions and signals which are accessible within the entity and the corresponding architectures. In the region between the keywords begin and end passive statements and procedures can be called. Passive means that no signal assignment neither in this procedure nor in any procedure called within the procedure is allowed. Passive statements could be used to generate warnings, for example, in case of setup and hold time violations on the inputs of a flip-flop.


next up previous contents
Next: 2.3 Architecture Up: 2. Basic VHDL Concepts Previous: 2.1 Components of a
Richard Geissler
1998-10-07